Delay-locked loop

ABSTRACT

This invention relates to a delay locked loop comprising a line of delay cells (R 1 , R 2 , . . . , Rn) mounted in series, the delay signal output by the loop being output from the output of one of the delay cells, the input of the delay cells line being connected to a first input of a phase/frequency detector ( 1 ), for which a second input is connected to an output from the delay cell.  
     The loop comprises control means ( 4 ) capable of modifying the output from the delay cell connected to the second input of the phase/frequency detector ( 1 ), at the rate of a clock signal (H) when stimulated by control information (I). The invention is particularly applicable to generating and measuring delays and for frequency synthesis in mobile applications.

TECHNICAL DOMAIN AND PRIOR ART

The invention relates to a Delay Locked Loop (DLL).

DLL loops are commonly used to put two clock signals into phasealignment, particularly in DRAM (Dynamic Random Access Memory) memories.DLL loops can then give very good synchronism between a clock externalto the integrated circuit and an internal clock. DLL loops are also usedto precisely generate or measure a time delay, or to generate signalsampling clocks (see “An Eight Channel 36GSample/s CMOS TimingAnalyser”, Dan Weinlader, Ron Ho, Chih-Kong Ken Yang, Mark Horowitz,2000 IEEE International Solid-Sate Circuits Conference).

The invention is applicable to all domains mentioned above, andparticularly advantageously, to generation and measurement of delays intransceivers using the ultra wide band type communication technique.

The schematic diagram for a DLL loop according to prior art is shown inFIG. 1. The DLL loop comprises a delay line composed of n delay cells Ri(i=1, 2, 3, . . . , n−1, n) in series, a phase/frequency detector 1, acharge pump 2 and a loop filter 3. Each delay cell introduces a delay Δtidentical to delays in other cells. The delay Δt may be controlled by asignal that may be a voltage or a current. Each delay cell may be madefrom a differential pair. The delay variation Δt is then obtained by thevariation of the polarisation current of the differential pair.

The input and output of the delay line are applied to thephase/frequency detector 1. The phase/frequency detector 1 may be asimple phase comparator that compares phases of input and output signalsof the delay line. The signal output from detector 1 controls the chargepump 2 that then generates a current that depends on the phasedifference between the input and output signals of the delay line. Thiscurrent is applied to the input of the loop filter 3 to be filtered. Thefiltered current output from the loop filter 3 is applied to the cellsof the delay line to control the delay of the cells.

The operating method of a DLL loop according to known art will now bedescribed.

A signal with period T is applied to the input of the delay line. Whenthe DLL loop is stable, the input and output signals of the delay lineare in phase. The delay between these two signals is then equal to T.Since all delay cells are identical, the delay added by a cell is equalto T/n. In addition to the clock signal applied to the input to thedelay line, there are then n clock signals ai (i=1, 2, 3, . . . , n−1,n), a signal ai being offset by the time interval iT/n with respect tothe clock signal applied to the input of the delay line. The differentsignals ai can be used to measure a delay, generate a delay, synthesisea frequency signal, reconstruct signals, etc.

One advantage of this type of structure is its low consumption. However,several disadvantages can be emphasised.

Thus, generating a delay mT/n can lead to the use of a large number n ofcells. For example, a delay of 13 T/100 (m=13 and n=100) will requirethe use of a hundred delay cells.

Furthermore, the structure is limited in frequency by the minimum delayTmin imposed by each elementary delay cell. When working at maximumfrequency, it is impossible to generate a delay that is not an integermultiple of Tmin.

The invention does not have these disadvantages.

PRESENTATION OF THE INVENTION

The invention relates to a delay locked loop comprising a line of delaycells mounted in series, a delay signal output by the loop being outputfrom the output of one of the delay cells, the input of the delay cellsline being connected to a first input of a phase/frequency detector, forwhich a second input is connected to an output from the delay cell. Thedelay loop comprises control means capable of modifying the output fromthe delay cell connected to the second input of the phase/frequencydetector, at the rate of a clock signal when stimulated by controlinformation.

The delay locked loop according to the invention can thus be used tomodify the number of delay cells seen by the phase/frequency detector.This modification produces an elementary delay of each delay celldifferent from the elementary delay T/n obtained according to prior art.

As will become clearer in the remainder of the description, the delay ofan elementary delay cell may then be a fractional delay. It is thuspossible to obtain a fractional DLL loop.

A modification in the number of delay cells seen by the phase/frequencydetector may be made at every clock tick of the signal applied to theinput of the delay line. This modification may also be made at a lowerfrequency.

The use of a number of delay cells lower than the total number of delaycells available also has the advantage that it reduces consumption ofthe DLL loop. Furthermore, the maximum working frequency is increasedsince this maximum frequency is inversely proportional to the quantityN.Tmin, where N is the number of delay cells used and Tmin is theminimum delay input by an elementary delay cell.

BRIEF DESCRIPTION OF THE FIGURES

Other characteristics and advantages of the invention will becomeclearer after reading a preferred embodiment of the invention made withreference to the appended figures, wherein:

FIG. 1 shows a delay locked loop according to prior art;

FIG. 2 shows a delay locked loop according to a first embodiment of theinvention;

FIG. 3 shows an example of a delay locked loop according to the firstembodiment of the invention;

FIG. 4 shows a delay locked loop according to a second embodiment of theinvention;

FIGS. 5 a and 5 b respectively show an improvement to the delay lockedloop according to the first embodiment of the invention and animprovement to the delay locked loop according to the second embodimentof the invention.

The same references denote the same elements in all figures.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

FIG. 1 has already been described; therefore there is no point indescribing it again.

FIG. 2 shows a delay locked loop according to a first embodiment of theinvention.

Apart from the elements already mentioned in the description in FIG. 1,a DLL loop according to the first embodiment of the invention comprisesmultiplexing means 4. The multiplexing means 4 comprise n signal inputs,one signal output, one clock input and one control input.

Each signal input of the multiplexing means 4 is connected to adifferent delay signal ai (i=1, 2, . . . , n). The signal output isconnected to one of the inputs of the phase/frequency detector 1. Thesignal applied to the input of the phase/frequency detector 1 among thesignals applied to the input of the multiplexer, is determined by aclock signal H applied to the clock input and by information I appliedto the control input. At each tick of the clock signal H, the signalapplied to the phase/frequency detector is chosen as a function of theinformation I. The information I thus selects the sequence of signalsthat are applied to the input of the phase/frequency detector, at therate of the clock signal H.

The clock signal H may be the same signal as the clock signal applied tothe input of the delay line, or it may be a different clock signal. Theinformation I may be periodic or non-periodic information.

In general, the number of delay cells seen by the phase/frequencydetector can change at each clock tick of the clock signal H or at alower frequency. This modification may be applied such that the averagevalue of the number of delay cells seen by the phase/frequency detectoris chosen in advance as a function of the required fractional delay. Forexample, the average value of the number of delay cells seen by thedetector may be obtained by taking a weighted average and using thenumber of clock ticks of the clock H during which the number of delaycells is effective, as weighting for each delay cell. In this case thereis a relation between the average number NC of delay cells used and thedelay Δt of an elementary cell, namely:Δt=T/NC

We will now describe a non-limitative example as an illustration of theperformances of a DLL loop according to the invention. We will considera delay line that comprises ten delay cells (n=10). It is assumed thatthe clock H that controls multiplexing is identical to the clock that isapplied to the input of the delay line, except for a delay. The signalapplied to the phase/frequency detector is different from the inputfrequency at each clock tick. In this example, it is also assumed thatthe signal selected by the information I to be applied to the input ofthe phase/frequency detector is an alternation of signals a10 and a9.The average phase that is compared by the phase/frequency detector isthen equal to 9.5 Δt, where Δt is the delay of one elementary cell.Therefore, we obtain the relation:Δt=2 T/19

It is then possible to generate delays equal to 2 T/19, 4 T/19, . . . ,18 T/19 with a line of ten delays. Nineteen delays would be necessary toobtain the same result using a DLL loop according to prior art.

We will now describe more generally how to generate any delay startingfrom a simple fractional DLL loop. A simple fractional DLL loop means aDLL loop that only uses two successive delay signals, for examplesignals an-1 and an, for multiplexing.

It is assumed that signals an-1 and an are used during p clock ticks andq-p clock ticks respectively. The average value of the delay added bythe delay line is then equal to (n−p/q)Δt. The value of the delay of anelementary cell is then given by the relation:Δt=q T/(qn−p)

Therefore as a non-limitative example, for a delay line comprising tendelay cells and assuming that I is a periodic signal with period 100 T(q=100 and the average value of a delay is then obtained on 100 points),the result is then:Δt=100 T/(1000−p)

An evaluation of the number p then gives:P=PART[1000−100 T/Δt]where PART[X] represents the integer part of X.

To make a fractional delay equal to aT/b at the output from the rank kdelay cell, in which a and b are two arbitrary integer numbers, we needto set:kΔt=a T/b, namelya T/b=k q T/(q n−p)

Therefore, the result is a system of 2 equations with 4 unknowns p, q, nand k, each unknown being an integer number. There are always solutionsto a system of equations like this.

For example, to obtain a delay equal to 13 T/100, the solution is asfollows:p=4, q=13, n=8, k=1

The delay 13 T/100 is then obtained with only eight delay cells. Thisresult should be compared with the result obtained according to priorart in which 100 delay cells are necessary (see above).

Another example could be given for obtaining a delay of 14 T/121. Thefollowing solution is then obtained:p=5, q=7, n=18, k=2

In this example, the number of cells could be even further reduced bythe following solution:p=5, q=14, n=9, k=1

In this case nine cells are advantageously sufficient.

An example of the DLL loop according to the first embodiment of theinvention will now be described with reference to FIG. 3.

According to the example in FIG. 3, the multiplexing means 4 comprise amultiplexer 5 and a sigma delta modulator 6. The sigma delta modulator 6comprises a clock input and a signal input. The clock signal H isapplied to the clock input and the information I is applied to thesignal input. The sigma delta modulator 6 converts the information Iinto a digital control signal C, at the rate of the clock signal H. Thedigital control signal C controls switching of the multiplexer 5. Oneexample of the use of a sigma delta modulator is that it reduces thenoise of the switching control information.

For example, in the case of a simple fractional DLL loop, theinformation I applied to the sigma delta modulator to generate a correctsequence of signals to be applied to the phase/frequency detector, isequal to a fractional value p/q, as mentioned above. The signal C outputfrom the modulator may be in two different states (a+1 state to choosethe signal an and a 0 state to choose the signal an-1) such that theaverage value of signal C is equal to p/q, except for the quantificationerror (however, this quantification error can be reduced by optimisingthe modulator). It is then possible to obtain an average loop delayequal to the quantity (n−p/q) Δt, which is the objective.

A DLL loop according to the first embodiment of the invention isobviously not limited to the example of the simple fractional DLL loopmentioned above. More generally, the use of a sigma delta modulator witha multibit quantifier results in a choice between n delay outputs fromthe DLL loop, where n is a number equal to or greater than 2.

It is also possible according to the invention to apply variableinformation I to the input of the sigma delta modulator. The result isthen a delay or frequency modulated by a variable magnitude contained inthe information I. The number NC of delay cells used is then a variablemagnitude that modulates the delay Δt of an elementary cell. Theinvention can thus be used to generate a variable delay used to generatea PPM (Pulse Position Modulation) signal used in the UWB (Ultra WideBand) technology.

FIG. 4 shows a second embodiment of a delay locked loop according to theinvention.

Apart from the circuits shown in FIG. 1, the delay locked loop in FIG. 4comprises a first set of switches Iqi (i=1, 2, . . . , n), a second setof switches Ipi (i=1, 2, . . . , n) and a control circuit 7. Each switchIpi is placed at the output from the delay Ri and each switch Iqi isplaced in parallel with the assembly formed by the delay Ri and theswitch Ipi.

The switches Ipi and Iqi are controlled by control signals pi and qirespectively. The control circuit 7 comprises a clock input and acontrol input on which a clock signal H and a control signal Irespectively are applied. The signals pi and qi are output from thecontrol circuit 7. At each tick of the clock H, the control circuit 7outputs a combination of control signals pi, qi capable of opening orclosing the corresponding switches Ipi, Iqi. It is then possible tosubtract one or several arbitrary delays from the delay loop. If theoutput from the delay loop has to oscillate, for example between signalsan and an-1, it is then possible to alternately short circuit each ofthe delay cells using an algorithm adapted to this purpose (randomalgorithm, noise formatting algorithm, etc.). This advantageouslyreduces the influence of the dispersion in delays between each delaycell. For example, in the case in which the delay of the last delay cellRn is significantly different from the delay of the other cells, theinfluence of this cell will be different from the influence of the othercells due to its switching external to the loop.

A delay locked loop according to the second embodiment of the inventionhas the same advantages as a delay locked loop according to the firstembodiment. As a non-limitative example, it is thus possible to make asimple fractional DLL loop using two successive delay signals, forexample signals an-1 and an. The value of the delay Δt of an elementarycell is then given by the relation:Δt=q T/(qn−p),where magnitudes p, q, n and T are the previously defined magnitudes.

Similarly, the control circuit 7 may be composed of a sigma deltamodulator and a digital control signal (not shown on the figures). Theclock signal H and the control signal I are applied on the sigma deltamodulator and a digital control signal C output by the sigma deltamodulator is applied to the digital control circuit.

According to one improvement to the second embodiment of the invention,switches and switchable loads can be added at the input and output ofthe different delay cells such that the number of switches passedthrough is always the same regardless of the programmed delay, and eachdelay cell always sees the same load on its input and on its output.

Within the context of making a delay locked loop using the silicontechnology, and regardless of the embodiment of the invention, theprecision of the generated delay or the synthesised frequency depends onthe matching that exists between the different delay cells. The numberof delay cells in a locked loop according to the invention issignificantly lower than the number of delay cells in a locked loopaccording to prior art, therefore the propagation time constraint for anelementary delay cell can be reduced. It is then possible to increasethe surface area of components used to make an elementary delay cell,which advantageously increases the precision of the loop.

Similarly, regardless of its embodiment, a delay locked loop accordingto the invention can advantageously be used to generate delays that arenot integer multiples of the minimum time Tmin, while working at themaximum working frequency.

In general, the large number of degrees of freedom in a DLL loopaccording to the invention compared with the number of degrees offreedom in a DLL loop according to prior art makes it possible to extendand very significantly improve loop performances.

The invention is advantageously made using conventional VLSI siliconintegration techniques.

FIGS. 5A and 5B show an improvement to the phase locked loop accordingto the first embodiment and the second embodiment respectively of theinvention.

The operation of a delay locked loop includes two distinct phases: alatching phase and a phase during which the elementary time no longervaries.

The delay generated by each cell in the delay loop has a lower limit andan upper limit. A convergence problem can then arise during the latchingphase, particularly when latching constraints are severe. Thisconvergence problem may also arise due to the large dispersion ofelementary times of the different cells when the delay locked loop ismade using the silicon technology. A delay locked loop can then be in alocked state during the latching phase, when the minimum delay of eachcell is reached and the global delay is still too high. The delay lockedloop according to the improvement to the invention represented in FIGS.5A and 5B eliminates this disadvantage.

According to the improvement to the invention, the delay locked loopcomprises a convergence analysis device 8, a switch 9 and a processingcircuit 10, in addition to the elements described above. The input tothe convergence analysis device 8 is connected to the output from thephase/frequency detector 1. The switch 9 comprises two signal inputs, acontrol input and an output. A first input to the switch signal 9 isconnected to the output from the convergence analysis device 8 while theinformation I mentioned above is applied to the second signal input. Theoutput from switch 9 is connected to the input to the processing circuit10, the output from which is connected to the control input of themultiplexing means 4 (case in FIG. 5A) or to the control input of thecontrol circuit 7 (case in FIG. 5B).

The convergence analysis device 8 outputs information on its output thatmeasures the stability and convergence state of the loop. Theconvergence analysis device 8 also outputs the control signal of switch9.

During the latching phase, the switch 9 is controlled such that theoutput from the convergence analysis device 8 is connected through theprocessing circuit 10 to the control input of the multiplexing means 4(case in FIG. 5A) or to the control input of the control circuit 7 (casein FIG. 5B). The processing circuit 10 uses convergence informationoutput from the device 8 to notify the multiplexing means 4 or thecontrol circuit 7 whether it should increase or reduce the number ofcells in the loop. The signal S output from the processing circuit 10then constitutes a control used to select a number of delay cells thatcan prevent the loop from getting locked.

When the latching phase is complete, the switch 9 is controlled suchthat the input of the processing circuit 10 is connected to theinformation I mentioned above. The information I is then processed bythe circuit 10 as a function of the number of delay cells selectedduring the latching phase. Therefore, the processing circuit 10 willpreviously have memorised the number of cells selected to obtainconvergence. The signal S applied to the control input of themultiplexing means 4 (case in FIG. 5A) or the control input of thecontrol circuit 7 (case in FIG. 5B) is then obtained starting frominformation I and the number of memorised cells.

1. A delay locked loop comprising a line of delay cells (R1, R2, . . . ,Rn) mounted in series, a delay signal output by the loop being outputfrom the output of one of the delay cells, the input of the delay cellsline being connected to a first input of a phase/frequency detector (1),for which a second input is connected to an output from the delay cell,characterised in that the loop comprises control means (4, 7) capable ofmodifying the output from the delay cell connected to the second inputof the phase/frequency detector (1), at the rate of a clock signal (H)when stimulated by control information (I).
 2. Delay locked loopaccording to claim 1, characterised in that the control means comprisemultiplexing means (4) with n inputs and one output, each input of themultiplexing means (4) being connected to one different delay celloutput, the output from the multiplexing means being connected to thesecond input of the phase/frequency detector.
 3. Phased locked loopaccording to claim 2, characterised in that the multiplexing means (4)comprise a multiplexer (5) and a sigma delta modulator (6) with a clockinput on which said clock signal (H) is applied and a signal input onwhich said control information (I) is applied, the sigma delta modulator(6) outputting a digital control signal applied to the multiplexer (5).4. Delay locked loop according to claim 1, characterised in that thecontrol means comprise a first set of switches Iqi (i=1, 2, . . . , n),a second set of switches Ipi (i=1, 2, . . . , n) and a control circuit(7) with a clock input on which said clock signal (H) is applied and acontrol input on which said control information (I) is applied, theswitch Ipi being placed at the output from the rank i delay cell Ri andthe switch Iqi being placed in parallel with the assembly formed by therank i delay cell Ri and the switch Ipi, switches Ipi and Iqi beingcontrolled by control signals pi and qi respectively output from thecontrol circuit (7).
 5. Delay locked loop according to claim 4,characterised in that switches and switchable loads are placed at theinput and output of the different delay cells (R1, R2, . . . , Rn) suchthat the total number of switches used in the loop during operation ofthe loop is always the same, and each delay cell always sees the sameload on its input and on its output.
 6. Delay locked loop according toclaim 4, characterised in that the control circuit (7) comprises a sigmadelta modulator with a clock input on which said clock signal (H) isapplied and a signal input on which said control signal (I) is appliedand a digital control circuit on which a digital control signal outputby the sigma delta modulator is applied.
 7. Delay locked loop accordingto claim 1, characterised in that the control information (I) is afractional value p/q such that the output from the delay line iscomposed of the output from the rank n−1 delay line for p clock ticksand the output from the rank n delay line during q clock ticks, where pand q are two integer numbers and q is greater than p, and the value ofthe delay of a delay cell is given by the relation:Δt=q T/(qn−p), where T is the period of a signal applied to the input ofthe delay line.
 8. Delay locked loop according to claim 1, characterisedin that the clock signal (H) is identical to a signal applied to thefirst input of the phase/frequency detector (1), except for a delay. 9.Delay locked loop according to claim 1, characterised in that the clocksignal (H) is a signal with a period less than the period of the signalapplied to the first input of the phase/frequency detector (1). 10.Delay locked loop according to claim 1, characterised in that itcomprises means (8, 9, 10) to select a number of delay cells such thatthe loop will not get locked, during a loop latching phase.
 11. Delaylocked loop according to claim 10, characterised in that the means (8,9, 10) provided to select the number of delay cells to prevent the loopfrom getting locked, during a loop latching phase, comprise aconvergence analysis device (8), a switch (9) and a processing circuit(10), the input to the convergence analysis device (8) being connectedto the output from the phase/frequency detector (1), the switch (9)being controlled such that the output from the convergence device (8) isconnected to the input to the processing circuit (10), the output fromthe processing circuit (10) being connected to a control input of thecontrol means (4, 7).
 12. Delay locked loop according to claim 10,characterised in that it comprises means (10) of memorising the selectednumber of delay cells.